This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-232115, filed on Jul. 31, 2000; the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor device and, more particularly, to shallow trench isolation (STI) that is a technique using a shallow trench for isolation of device regions.
Semiconductor devices are moving on toward miniaturization and high integration to meet the requirements of lower power consumption, higher function and higher performance. In accordance with such movements, miniaturization processes have been developed, and they are contributing to improvements of device performance and progresses of LSI toward higher function and higher performance by high integration. Among miniaturization techniques, those for shorter wavelengths of light in lithography and progress of very high resolution techniques such as phase shifting for compensating shorter wavelengths are especially remarkable.
In contrast, regarding device isolation structures, there was a change in applied process upon the 0.25 xcexcm process generation as a boundary. That is, although LOCOS employing selective oxidation process was conventionally used, device structure has been moved to STI (shallow trench isolation) intended for more miniaturization since the 0.25 xcexcm process generation. STI is a technique of obtaining a device isolation structure by first making a shallow trench at a surface part of a Si substrate through a micro process and then filling an insulating film therein.
FIGS. 9A and 9B show cross-sectional structures of typical STIs. These structures include an insulator 12 filled in a trench 11 formed along a surface part of a substrate 10, and a boundary between a p-well 13 and an n-well 14 is positioned immediately under STI.
In case of FIG. 9A, an n+diffusion layer 15, which is a device region, is formed on the surface part of the p-well 13, but no device region exists in the opposite position in the n-well side. This is called an open space.
In FIG. 9B, however, an n+diffusion layer 15 is formed as the device region on the surface part of the p-well 13, and a p+diffusion layer 16 is also formed as a device region on the surface part of the n-well 14 in the opposite position. This is called a narrow space.
In case of the narrow space, the tapered angle of the wide wall of the trench 11xe2x80x2 is steeper than that in case of the open space as shown in FIG. 9B. It is generally assumed that this is a result of a loading effect.
In the explanation below, distance between the trench end position and the boundary of the well is defined as the well boundary distance, and distance between isolated device regions is defined as the well isolation distance. The well isolation distance is equal to the width of STI.
FIG. 10 is a graph that shows relations between the width of STI and the tapered angle in a device where each device region is formed inside a well to be isolated. According to this graph, as the width of STI decreases, the tapered angle tends to become steeper. This is because etching products that will form the etching protective film adhere onto side walls of the region to be etched during RIE (reactive ion etching) for making the trench and the quantity of the etching products changes with the area of the region to be etched.
If the tapered angle of the trench wide wall becomes steeper, then the leak path extending from the device region 16 along the side surface 12a and the bottom surface 12b of the trench to the p-well 13 (creepage distance) becomes longer as shown in FIG. 11.
FIGS. 12A and 12B show results of an experiment in actual formation of devices. FIG. 1lA shows those of devices in which device regions are not opposed whereas FIG. 12B shows those of devices in which device regions are opposed. This result shows that, in devices where device regions are not opposed, the withstand voltage property decreases to an unusable level when the STI width reaches 0.2 xcexcm, but in devices where device regions are opposed, they maintains a sufficient withstand voltage even under 0.2 xcexcm.
Thus, in LSI having a STI structure, the tapered angle of the trench side wall is steeper in case of a narrow space as compared with the case of an open space.
On the other hand, well isolation property in LSI depends on how effectively isolated are devices on the STI side surface, bottom surface and Si surface. Therefore, in miniaturization of LSI, integrated circuits designed and disposed in various modes have to be designed on the basis of a result of the open space, and this is a serious disadvantage in terms of miniaturization.
To improve the well isolation property, it is impurity concentration of the well may be increased, in general. However, although the isolation property is certainly improved, there arises another problem that the junction capacitance increases and adversely affects from the viewpoint of high-speed operation.
A semiconductor device according to an embodiment of the present invention comprises:
first and second wells opposite in conductivity type and adjacent to each other;
a well isolation structure in form of a shallow trench formed on the boundary of said first and second wells, said well isolation structure having a first width and a second width larger than the first isolation width;
a first device region provided in said first well; and
a second device region provided in said second well, wherein said first and second device regions are provided so as to be opposed at said first width of said well isolation structure and wherein said first and second device regions do not meet facing at said second width of said well isolation structure.
A method of manufacturing semiconductor device comprises:
forming a first well of a first conductivity and a second well of a second conductivity which is opposite to the first conductivity in a manner they are disposed adjacent to each other;
forming a well isolation structure in a form of a shallow trench on the boundary of said first and second wells, said well isolation structure having a first width and a second width which is larger than the first width;
forming a first device region in said first well; and
forming a second device region provided in said second well, wherein said first and second device regions are provided so as to be opposed at said first width of the well isolation structure and wherein said first and second device regions do not meet facing at the second width of said well isolation structure.